Field of the Invention
The present disclosure relates to a power control device and method and an organic light emitting display device including the same.
Discussion of the Related Art
An active matrix type organic light emitting display device includes a self-luminous organic light emitting diode (OLED) and has many advantages such as fast response speed, high emission efficiency, high luminance, and wide viewing angle.
An OLED typically includes an anode electrode, a cathode electrode, and organic compound layers (hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL)) formed therebetween. The organic compound layers include the HIL, HTL, EML, ETL, and EIL. When a driving voltage is applied between the anode electrode and the cathode electrode, holes which have passed through the HTL and electrons which have passed through the ETL move to the EML to form excitons, resultantly causing the EML to emit visible light.
In an organic light emitting display device, pixels each including an OLED are arranged in a matrix, and the brightness of each pixel is adjusted according to a gray level of video data. Each pixel may include a driving thin film transistor (TFT) DT for controlling a driving current applied to the OLED and a switching unit SC for programming a voltage (hereinafter, referred to as “Vgs”) between a gate and a source of the driving TFT DT. The driving TFT DT generates a current (hereinafter, referred to as “Ids”) between a drain and a source according to the programmed Vgs, and supplies Ids as a driving current to the OLED. Here, a high potential driving power (hereinafter, referred to as “VDDEL”) and a low potential driving power (hereinafter, referred to as “VSSEL”) are applied to each pixel in order to generate a driving current. An emission amount of the OLED is determined depending on the driving current.
A voltage level of VDDEL is designed to be positioned within a saturation section RG2 on a Vds−Ids plane as illustrated in FIG. 2 in order to secure stability of an operation regarding the driving TFT.
The saturation section RG2 refers to a voltage section in which Ids is not substantially changed in spite of a change in Vds, and is positioned on the right of a boundary point BP on the Vds−Ids plane.
The active section RG1, which is different from the saturation section RG2 with respect to the boundary point BP, refers to a voltage section in which Ids changes according to a change in Vds, and is positioned on the left of the boundary point BP on the Vds−Ids plane.
To allow the driving TFT to constantly operate in the saturation section RG2 in consideration of a process variation of a display panel, VDDEL is determined to have a sufficient voltage margin value Vmg from the boundary point BP as illustrated in FIG. 2. After being determined as a fixed value, VDDEL is commonly applied to every pixel.
Meanwhile, luminance implemented in each pixel is affected by an ambient temperature as illustrated in FIG. 3. When an ambient temperature is lowered in a state in which Vgs of the driving TFT and VDDEL are constant, brightness is also lowered. Such brightness deviation results from the fact that electron mobility properties of the driving TFT are proportional to temperature. The brightness deviation becomes severe as an ambient temperature is lowered. When the brightness deviation is severe, display quality of an image is degraded.
In order to compensate for a brightness deviation according to temperature, a technique of changing a voltage level of FDDEL through a S-wire interface scheme as illustrated in FIG. 4 is known. In the S-wire interface scheme, a power control signal SCON generated by a controller is transmitted to a power management integrated circuit (PMIC) through a single transmission line (or a single wire). The controller differently generates the number of transition pulses included in the power control signal SCON according to temperature. Then, the PMIC counts the number of transition pulses included in the power control signal SCON during a unit time, and adjusts a voltage level of VDDEL according to the counted value. In FIG. 4, PMIC_EN is a control signal for activating an operation of the PMIC.
The related art VDDEL adjustment technique may not have a matching process for determining whether the power control signal SCN output from the controller and the power control signal SCN received by the PMIC match. Thus, if noise is introduced to the power control signal SCON, the PMIC outputs an abnormal voltage due to an influence of noise and a voltage level of VDDEL may then be adjusted to an undesired value.